Laterally diffused metal oxide semiconductor (LDMOS) transistors are often used as power switch devices.
FIG. 1a is a schematic illustration of an existing n-type LDMOS device. The device includes a p-type doped region 11 and an n-type drift region 12, laterally neighboring each other and both formed in a p-type substrate (or epitaxial layer) 10. The n-type drift region 12 has a planar top surface. A heavily doped n-type source region 19 is formed in a central portion of the p-type doped region 11. A gate oxide layer 13 has its one end on the n-type drift region 12, the other end on the heavily doped n-type source region 19, and the rest portion on the p-type doped region 11. A gate 14 is located on the gate oxide layer 13. Sidewalls 15 are formed on both sides of the gate oxide layer 13 and the gate 14. A heavily doped n-type drain region 20 is formed at one end of the n-type drift region 12 farther from the p-type doped region 11. A p-type heavily doped pick-up region 21 is formed at one end of the p-type doped region 11 farther from the n-type drift region 12. A channel of the LDMOS device is formed in a portion of the p-type doped region 11 under the gate oxide layer 13. A p-type LDMOS device has a similar architecture to the n-type LDMOS device discussed above expect that all components of the p-type LDMOS device have conductivity types opposite to their counterparts in the n-type LDMOS device.
The n-type LDMOS device in FIG. 1a may be modified into a p-type LDMOS device by including an n-type well in the p-type substrate (epitaxial layer) 10, encircling both an n-type doped region 11′ and a p-type drift region 12′, and converting the conductivity types of all the rest components of the n-type LDMOS device to respective opposite types of conductivity.
The above-mentioned device is a non-channel-isolated LDMOS device, which may be modified into a channel-isolated n-type LDMOS device by including an n-type well in the p-type substrate (epitaxial layer) 10, encircling both the p-type doped region 11 and the n-type drift region 12, and remaining the same structure and conductivity type of all the rest components of the n-type LDMOS device shown in FIG. 1a. 
In order to reduce power consumption, an LDMOS device is typically required to have an on-resistance as low as possible. Thus, during the design of the device, it is contemplated to reduce the physical length of the drift region (i.e., the length A shown in FIG. 1a) to a possible minimum and/or to increase the doping concentration of the drift region, so as to reduce the series resistance of the drift region. However, on the other hand, as all LDMOS devices are high-voltage devices and the value of the breakdown voltage is an important characteristic parameter, the LDMOS devices are also required to have a high breakdown voltage by owning a relatively great drift region length and a low drift region doping concentration. Thus, it is obvious that the on-resistance and the breakdown voltage have to be compromised. It is difficult for an existing LDMOS device to have both a low on-resistance and a high breakdown voltage.